1. Field of the Invention
The present invention relates to an apparatus for electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) technologies and, more particularly, to a low triggering voltage partially-depleted (PD) SOI silicon-control-rectifier (SCR) structure.
2. Description of the Prior Art
Metal oxide semiconductor field effect transistor (MOSFET) scaling on bulk silicon has been the primary focus of the semiconductor and microelectronic industry for achieving complementary metal oxide semiconductor (CMOS) chip performance and density objectives. The shrinking of MOSFET dimensions for high density, low power and enhanced performance requires reduced power-supply voltages. Because power consumption (P) is a function of capacitance (C), power supply voltage (V), and transition frequency (f), in accordance with the expression P=CV.sup.2 f, the focus has been on reducing both C and V as the transition frequency f increases. As a result, dielectric thickness and channel length are scaled with power-supply voltage. Power-supply reduction continues to be the trend for future low-voltage CMOS. However, with power supply reduction, transistor performance is severely impacted by both junction capacitance and the MOSFET body effect at lower voltages. As technologies scale below 0.25 .mu.m channel lengths, to 0.15 and 0.1 .mu.m, short-channel effects (SCE) control, gate resistance, channel profiling and other barriers become an issue for advanced CMOS technologies. While significant success has been achieved with successive scaling of bulk CMOS technology, the manufacturing control issues and power consumption will become more difficult with which to deal.
Using silicon-on-insulator (SOI) substrates, many of the concerns and obstacles of bulk-silicon CMOS can be eliminated at low power supply voltages. CMOS-on-SOI has significant advantages over bulk CMOS technology and will achieve the scaling objectives of low power and high performance for future technologies. CMOS-on-SOI provides low power consumption, low leakage current, low capacitance diode structures, good sub-threshold I-V characteristics (better than 60 mV/decade), a low soft error rate from both alpha particles and cosmic rays, good static random access memory (SRAM) access times, and other technology benefits. SOI process techniques include epitaxial lateral overgrowth (ELO), lateral solid-phase epitaxy (LSPE) and full isolation by porous oxidized silicon (FIPOS) as are known in the art.
SOI has not become a mainstream CMOS technology in view of the rapid improvement in bulk CMOS technology performance. However, SOI is a contender for mainstream CMOS applications. One of the barriers to implementing SOI as a mainstream CMOS technology is the "floating body" issue. Another barrier is electrostatic discharge protection (ESD). With respect to ESD protection, one problem with SOI is that there are no diodes natural to the process that are not in the presence of a polysilicon gate edge. The primary reason this is a concern is that electrical overload of the polysilicon gate structure occurs as well as the high capacitance per unit length in the SOI MOSFET structure.
An ESD protection circuit that includes a silicon-control-rectifier (SCR) is considered to have very good electrostatic discharge performance. Since the SCR ESD protection circuit has a low snap-back holding voltage of about 1-5 volts and a low effective resistance of about 1-3 Ohms, it provides a very good discharge condition for the electrostatic current. Referring to FIG. 1A, an SCR is placed in between an Input/Output pad 10 and an internal circuit 11 to be protected. The internal circuit 11 is tied to the Input/Output pad 10 via a conducting line 12. An SCR device serves as the main component in a protection circuit. In the drawing, the SCR device consists essentially of a pnp bipolar junction transistor T.sub.1 and an npn bipolar junction transistor T.sub.2. The collector of the pnp transistor T.sub.1 is connected together with the base of the npn transistor T.sub.2, forming a cathode gate identified by the node 13. The cathode gate 13 is coupled to the emitter of the npn transistor T.sub.2, via a spreading resistor R.sub.p, constituting a cathode 14 which is connected to a Vss terminal of the CMOS-on-SOI device. The base of the pnp transistor T.sub.1 is connected together with the collector of npn transistor T.sub.2 to form an anode gate identified by the node 15. The anode gate 15 is coupled to the emitter of the pnp transistor T.sub.1, via a spreading resistor R.sub.n, constituting an anode 16 which is connected to the conducting line 12.
A conventional PD-SOI (Partially-Depleted Silicon-on-Insulator) SCR cross-sectional view is shown in FIG. 1B, wherein there is an SOI substrate 20 including a thin film layer 21 separated from a bulk silicon substrate 22 by a buried oxide insulator 23. On top of the buried oxide insulator 23 two shallow trench isolation regions 24A and 24B are formed. Moreover, there are four conductivity regions in between those two shallow trench isolation regions and inside the thin film layer 21. These conductivity regions are P+ conductivity region 25, N conductivity region 26, P conductivity region 27, and N conductivity region 28, which form the conventional P.sub.+ -N-P-N.sub.+ structure of the PD-SOI SCR device.
However, there is one inherent constraining design factor for the PD-SOI SCR used in ESD protection circuits for sub-micron semiconductor devices. The triggering voltage for SCRs in PD-SOI devices is in the range of 30 to 50 volts. The typical thickness of gate oxide layers in CMOS fabrication processes employing a resolution of 0.6-0.8 microns is about 150-200 angstroms. Considering a dielectric breakdown strength of 10 MV/cm for typical SiO.sub.2 material, the gate oxide layers in these CMOS devices would be destroyed by a voltage of about 15-20 volts. Therefore, SCRs in PD-SOI devices with a trigger voltage in the range of 30-50 volts must be fitted with other protection components so that they can provide protection for gate oxide layers in CMOS on PD-SOI devices.
It is therefore an object of the present invention to provide an enhanced PD-SOI ESD protection performance apparatus for protecting internal circuits and particularly CMOS devices by reducing the trigger voltage required to turn on a protective PD-SOI SCR.